As demand for ever-shrinking semiconductor devices continues to increase, it has become particularly difficult to continue shrinking semiconductor devices, due to rapidly increasing costs associated with lithography and multiple process steps associated with pitch splitting techniques.
As device structures continue to decrease in size and become more complex, some of these structures may present challenges for detection of defects. For instance, a defect that is buried in a multilayer structure may be difficult to detect or characterize without destroying the device. Thus, there is a need for semiconductor wafer inspection systems for reliably and nondestructively detecting defects in multiple layer semiconductor devices, such as 3D NAND and DRAM memory and logic, as well as other complex structures that present defect detection challenges.